Technical Field
This disclosure relates generally to clocking circuitry and more specifically to feedback-controlled oscillators (e.g., phase-locked loops) arranged in two or more levels.
Description of the Related Art
Computer processing devices typically include sequential circuitry such as latches and flip-flops that are configured to perform various operations based on clock signal inputs. Driving clock signals to different portions of a circuit often consumes a significant portion of overall power consumption. As clock speed increases, reducing deviation from the desired clock periodicity (often referred to as “jitter”) in clock signals may become more important. Clock signals are typically controlled to a desired frequency using feedback-controlled oscillators, e.g., phase-locked loops (PLLs) or frequency-locked loops (FLLs). In some situations, multiple levels of feedback-controlled oscillators may be implemented to provide clock signals with low jitter characteristics. Each level in such a hierarchical configuration, however, may consume additional power.